1. Technical Field
The present application relates generally to an improved data processing system and method. More specifically, the present application is directed to a system that supports a full asynchronous interface within a memory hub device.
2. Description of Related Art
Contemporary high performance computing main memory systems are generally composed of one or more dynamic random access memory (DRAM) devices, which are connected to one or more processors via one or more memory control elements. Overall computer system performance is affected by each of the key elements of the computer structure, including the performance/structure of the processor(s), any memory cache(s), the input/output (I/O) subsystem(s), the efficiency of the memory control function(s), the main memory device(s), and the type and structure of the memory interconnect interface(s).
Extensive research and development efforts are invested by the industry, on an ongoing basis, to create improved and/or innovative solutions to maximizing overall system performance and density by improving the memory system/subsystem design and/or structure. High-availability systems, i.e. systems that must be available to users without failure for large periods of time, present further challenges related to overall system reliability due to customer expectations that new computer systems will markedly surpass existing systems with regard to mean-time-before-failure (MTBF), in addition to offering additional functions, increased performance, increased storage, lower operating costs, etc. Other frequent customer requirements further exacerbate the memory system design challenges, and include such items as ease of upgrade and reduced system environmental impact, such as space, power, and cooling.
Furthermore, with the movement to multi-core and multi-threaded processor designs, new requirements are being made for the memory subsystem to supply very large data bandwidths and memory capacity into a single processor memory module socket. At a system level, the bandwidth available from the memory subsystem is directly proportional to the number of memory channels that can be supported by the processor pin counts. Further, the capacity of the memory subsystem is limited by the number of memory devices that can be attached to a memory channel and still run within the power constraints of the memory subsystem. Thus, the goal at a system level is to balance the capacity, bandwidth, and power of the memory subsystem to achieve the best memory subsystem performance.
In known memory subsystem designs, the operating frequency of the memory channel frequency is linked to some multiple of the maximum supported operating frequency of the memory devices in the memory subsystem. For example, in a double-data (DDR) random access memory (RAM) design, the maximum operating frequency of the memory devices may be 800 MBits per second and the operating frequency of the memory channel may be 4 times that or 3.2 MBits per second. In another example, for the industry standard fully buffered dual in-line memory module (FB-DIMM) the channel frequency is 6 times the DRAM data rate. The link between the operating frequency of the memory channel and the operating frequency of the memory devices makes it difficult to optimize the capacity, bandwidth, and power for the memory subsystem. For example, as DRAM devices are added to a DIMM to increase the capacity of the DIMM, the additional electrical loading that results from the addition of the DRAM chips will result in a lower frequency of operation of the DRAM interface.
This reduction in frequency on the DIMM will result in a lower frequency on the memory channel as they are linked together by a fixed clock ratio. As in the example above, if the operating frequency of the DDR memory device is lowered to 400 MBits per second, the link between the memory device and the memory channel forces the memory channel data rate to drop to 1.6 Mbits per second or half the bandwidth of the previous example. This fixed ratio effectively results in a reduction of memory bandwidth as the memory capacity is increased. Additionally, a memory subsystem may want to choose to lower DRAM frequency for other reasons such as reducing the power consumption in the memory subsystem, lowering the cost of the memory devices, or the like. With the fixed ratio between the DRAM clock rate and the memory channel rate, this reduction in DRAM frequency results in a direct loss of bandwidth and system performance. Thus, the memory channel frequency link to the frequency of the memory devices presents a limiting factor for optimizing the capacity, bandwidth, and power for the memory subsystem.